1. Field of the Invention
The present invention relates to a solid-state image-capturing device, and the driving method thereof, and a camera, and particularly relates to a solid-state image-capturing device employing a CCD (Charge Coupled Device) type solid-state image-capturing device (hereafter, referred to as CCD image-capturing device) having an overflow drain (OFD) configuration, and the driving method thereof, and a camera.
The present invention also relates an electric charge transfer device, a solid-state image-capturing device, and a camera, and a driving method of a solid-state image-capturing device.
The present invention also relates a driving method and driving device for driving load such as capacitive reactance or inductive reactance or the like using a pulse signal, and electronic equipment to which this driving method and driving device are applied. More particularly, the present invention relates to an arrangement for reducing influence due to various types of variations or environmental variations at the time of performing pulse driving so as to have a predetermined transient speed, such that load output signals change gradually.
2. Description of the Related Art
Taking an n-type semiconductor substrate as an example, a p-type well region is formed on this n-type semiconductor substrate, and an n-type photoelectric conversion unit, i.e., a light receiving portion is further formed on the surface of this well region, and the image-capturing area of a CCD solid-state image capturing device comprises a plurality of the light receiving portions arrayed in a matrix manner.
The allowable amount of a signal charge e accumulated in the light receiving portions due to entrance of light with such a CCD solid-state image-capturing device, i.e., so-called handling charge amount of the light receiving portions, will be described with reference to FIGS. 1A and 1B.
FIGS. 1A and 1B are diagrams illustrating a potential distribution of light receiving portions for performing photoelectric conversion of a solid-state image-capturing device having a common vertical-type overflow drain configuration. FIG. 1A is a potential distribution diagram before regulation of a substrate voltage Vsub, and FIG. 1B is a potential distribution diagram after regulation of the substrate voltage Vsub.
As illustrated in the potential distribution diagrams in FIGS. 1A and 1B, the so-called handling charge amount of light receiving portions is determined with the height of potential barrier Φa of an overflow barrier OFB made up of a p-type well region.
That is to say, in the event that the signal charge e accumulated in light receiving portions exceeds the handling charge amount, the exceeding charge amount thereof exceeds the potential barrier Φa of the overflow barrier to overflow on the n-type substrate making up the overflow drain OFD, and is consequently discarded. Note that reference symbol “a” in FIGS. 1A and 1B indicates an oxide film on the light receiving portions.
This handling charge amount of the light receiving portions, i.e., the height of potential barrier Φa of the overflow barrier OFB is controlled with a bias voltage to be applied to the substrate serving as overflow drain, i.e., so-called substrate voltage Vsub.
However, with this configuration, the height of the potential barrier Φ of the overflow barrier OFB varies for each chip such as shown in a dashed line in FIG. 1A due to the manufacturing variations of the devices, and moreover, even the same chip varies regarding each light receiving portion. Now, with a solid-state image-capturing device, it is necessary for the maximum amount of signal charge (saturated signal amount) accumulated in the light receiving portions to be equal to or greater than a certain specification value from the perspective of quality management, and accordingly, let us say that the substrate voltage Vsub of a certain chip is set to a substrate bias voltage Vsub such that all of the light receiving portions within the chip can exhibit a saturation signal amount satisfying the above specification.
An emitter follower circuit is formed in a circuit for setting this substrate bias voltage Vsub, and various types of substrate voltage setting circuits including an emitter follower circuit have been proposed (e.g., see Japanese Unexamined Patent Application Publication No. 8-32065, Japanese Unexamined Patent Application Publication No. 2004-328203, and Japanese Patent No. 3440722).
FIG. 2 is a diagram illustrating the schematic configuration of a solid-state image-capturing device on which is mounted a basic substrate bias voltage setting circuit.
As illustrated in FIG. 2, a CCD chip 1 making up a solid-state image-capturing device is provided with a substrate bias setting circuit 2.
The substrate bias setting circuit 2 includes an NPN transistor 3 forming an emitter follower, a bias circuit 4, a resistance element 5, and a coupling capacitor 6.
The collector of the transistor 3 is connected to a power potential VDD, the base thereof is connected to the bias circuit 4 for generating a predetermined voltage due to resistance partial pressure, and the emitter thereof is connected to ground GND via the resistance element 5.
The connection point between the emitter of the transistor 3 and the resistance element 5 is connected with the coupling capacitor 6, and so-called electronic shutter pulses ΦSUB are applied from a terminal for inputting current pulses in the substrate bias voltage Vsub for shutter pulses supplied from outside of the substrate via the coupling capacitor 6 from between the emitter of the transistor 3 and the resistance element 5.
Here, when electrons flow into the emitter follower circuit, and the electrons pass through the PN junction within the transistor, the electrons are accelerated due to electric field to collide with silicon crystal lattices, thereby discharging secondary electrons and photons. At this time, in the event that the emitter follower circuit is provided around a pixel area, a phenomenon has been confirmed wherein the secondary electrons and photons enter inside of the pixel area of the CCD chip, and these are detected as noise.
That is to say, as illustrated with a schematic diagram in FIG. 3, with a region affected by the secondary electron and photon indicated by the reference symbol “A” in FIG. 3, and a region illustrated with the reference symbol “C” in FIG. 3 where the pixel area of the CCD chip illustrated with the reference symbol “B” in FIG. 3 is overlapped, the secondary electron is mixed therein as pixel charge, whereby the regions appear to emit light, or the photon is mixed in the pixel area to be photoelectrically converted, whereby the regions also appear to emit light, which have been confirmed as abnormality in image quality.
Particularly, in the event of shooting a night scene for example with a shooting mode whose exposure period is generally one second through several minutes or so (hereafter, referred to as long exposure mode), which is employed for shooting in darkness using a CCD camera, the above-described light emitting phenomenon due to the secondary electron and photon markedly appears. Note that with a normal shooting mode for performing shooting of 3 through 5 pictures per second (hereafter, referred to as normal exposure mode), the exposure period thereof is short, so the amount of the secondary electrons and photons occurring is small, and accordingly, a light emitting phenomenon does not reach a level recognized as abnormality in image quality.
There is occurrence of a dark current and so forth at the time of long exposure, and following capturing of a signal image, light shielding images are consecutively captured, and difference therebetween is taken, thereby performing elimination of noise of a fixed pattern in darkness.
A solid-state image apparatus, e.g., a two-phase driving method is employed for the horizontal transfer register of a CCD (Charge Coupled Device) area sensor.
FIG. 14 illustrates driving signal examples of two-phase driving. H1 and H2 denote diving pulses, RG denotes a reset gate pulse, and CCDout denotes output of a CCD.
Japanese Unexamined Patent Application Publication No. 2004-328203 has disclosed a basic two-phase driving technique employing a storage transfer configuration wherein emphasis is put on high performance.
With electric circuits and electronic equipment, various types of arrangement are employed wherein impedance components are regarded as load, and this load is driven with a pulse signal.
For example, examples of electronic equipment include an image-capturing device wherein CCD solid-state image-capturing devices having a transfer electrode serving as capacitive reactance are arrayed two-dimensionally. Also, there is a motor having a coil serving as inductive reactance.
On the other hand, when driving impedance components such as capacitive reactance or inductive reactance or the like as loads using a pulse signal, the phase and transition properties of a driving pulse is affected by the relation between the loads and a driving device, specifically relation between variations in the loads and variations in the device performance and environmental fluctuation, and as a result thereof, a problem occurs wherein it is difficult to drive these loads appropriately. In the event of low-speed driving, the influence thereof is small, but in the event of high-speed driving, a minute deviation sometimes causes great influence upon the performance.
Also, for example, in the event of driving multiple loads using pulse signals whose phases are shifted in small steps, a minute deviation of the respective phases sometimes prevents appropriate driving. Also, in the event of driving two loads using an inverted pulse signal as well, a minute deviation of the respective phases sometimes prevents appropriate driving.
Description will be made below using specific examples. With an image-capturing device having a transfer electrode serving as capacitive reactance, in recent years, with a video camera on which is mounted a CCD solid-state image-capturing device, there has been a strong demand for image-capturing a camera portion at high speed to perform slow playback regardless of a television system, and also with a digital still camera on which is mounted a CCD solid-state image-capturing device, deterioration in continuous shooting speed along with multiple pixilation has been seen as a problem, high-speed performance in an image-capturing device has been demanded.
FIGS. 49A and 49B are diagrams describing an arrangement of an existing image-capturing device. Here, FIG. 49A is a diagram illustrating principal parts in one configuration example of an existing image-capturing device employing a CCD solid-state image-capturing device of a interline transfer (IT) method, and FIG. 49B is a diagram illustrating one example of a driving method of a CCD solid-state image-capturing device.
An existing image-capturing device 1003 includes a CCD solid-state image-capturing device 1030, and a driving circuit 1004 serving as a driving device for driving the CCD solid-state image-capturing device 1030.
With the CCD solid-state image-capturing device 1030, multiple light receiving sensors 1031 serving as pixels are arrayed in a two-dimensional matrix manner. The CCD solid-state image-capturing device 1030 also includes an image-capturing portion (light receiving portion) 1030a wherein multiple vertical transfer registers 1033 having a CCD configuration are formed corresponding to each of the light receiving sensor rows. At the outside of the image-capturing portion (light receiving portion) 1030a, a horizontal transfer register 1034 having a CCD configuration is formed so as to connect to the last stages of the respective vertical transfer registers 1033, and the subsequent stage of the horizontal transfer register 1034 is connected with an output portion 36.
On the vertical transfer registers 1033 extending in the row (vertical) direction (light receiving surface side), four types of vertical transfer electrodes 1032 (each denoted with sub-numerals _1, _2, _3, or _4) extending in the horizontal direction so as to share the vertical transfer register 1033 at the same vertical position of each row are disposed in a predetermined sequence in the vertical direction so as to form opening portions on the light receiving surface of the light receiving sensors 1031.
The four types of vertical transfer electrodes 1032 are formed such that the two vertical transfer electrodes 1032 correspond to the one light receiving sensor 1031, and also are configured so as to transfer and drive signal charge in the vertical direction using four types of vertical transfer pulses ΦV_1, ΦV_2, ΦV_3, and ΦV_4 supplied from the driving circuit 1004. In other words, an arrangement is made wherein the two light receiving sensors 1031 are coupled as one pair (excluding the last stage of the horizontal transfer register 1034 side), and the vertical transfer pulses ΦV_1, ΦV_2, ΦV_3, and ΦV_4 are applied from the driving circuit 1004 to each of the four vertical transfer electrodes 1032.
With the example illustrated, at the horizontal transfer register 1034 side the vertical transfer electrodes 1032 are provided corresponding to one pair of the four vertical transfer registers 1033 in the vertical direction, in which the light receiving sensor 1031 positioned at the uppermost portion in the vertical direction corresponds to the vertical transfer electrode 1032_1 to which the vertical transfer pulse ΦV_1 is applied. The vertical transfer pulse ΦV_2 is applied to the vertical transfer electrode 1032_2 which is further one stage ahead (closer to the horizontal transfer register 1034 side), the vertical transfer pulse ΦV_3 is applied to the vertical transfer electrode 1032_3 which is further one stage ahead (closer to the horizontal transfer register 1034 side), and the vertical transfer pulse ΦV_4 is applied to the vertical transfer electrode 1032_4 which is the closest to the horizontal transfer register 1034 side.
The vertical transfer registers 1033 are connected to the horizontal transfer register 1034 via the last stage of one pair of the vertical transfer electrodes 1032 (transfer electrodes 32_1 through 32_4 to which the ΦV_1 through ΦV_4 are applied).
With the horizontal transfer register 1034, two horizontal electrodes 1035 (each denoted with sub-numerals _1 and _2) are formed so as to correspond to each of the vertical transfer registers 1033, and are configured so as to transfer and drive signal charge in the horizontal direction using two phases of horizontal driving pulses ΦH_1 and ΦH_2 supplied from the driving circuit 1004.
With the CCD solid-state image-capturing device 1030 having such a configuration, light is received and photoelectric-converted at the light receiving sensors 1031, and signal charge corresponding to the light receiving amount thereof is accumulated. The signal charge of the light receiving sensors 1031 is read out from the light receiving sensors 1031 to the vertical transfer registers 1033 during a vertical blanking period, and hereinafter, the signal charge is vertically transferred for each horizontal line during a horizontal blanking period, thereby performing vertical line shift to transfer the signal charge to the horizontal transfer register 1034. Subsequently, the signal charge transferred to the horizontal transfer register 1034 is transferred in the horizontal direction during a horizontal valid transfer period, and is externally output via the output portion 1036.
The vertical line shift of signal charge at an existing CCD solid-state image-capturing device 1030 has been designed so as to transfer and drive signal charge using the vertical transfer pulses (ΦV_1 through ΦV_4) during a horizontal blanking period Hb of a television system such as the driving timing of vertical line shift illustrated in FIG. 49B. Specifically, as illustrated in FIG. 49B, with vertical line shift of signal charge, for example, signal charge awaiting at the vertical transfer electrodes 1032_2 and 1032_3 corresponding to the ΦV_2 and ΦV_3 is line-shifted to the horizontal transfer register 1034 by the four types of vertical driving pulses ΦV_1 through ΦV_4. In other words, signal charge to the horizontal transfer electrode 1035_1 to which each of the horizontal driving pulses ΦH_1 of the horizontal transfer register 1034 is applied is transferred at the trailing edge of the vertical driving pulse ΦV_4 of the vertical transfer electrode 1032_4.
Though not illustrated in the drawing, the inclination of the leading and trailing edges ΔV/ΔT (ΔV denotes voltage, and ΔT denotes time) of the respective vertical driving pulses ΦV_1 through ΦV_4 which are applied to the vertical transfer electrodes 1032_1 through 1032_4 during the horizontal blanking period Hb at the time of vertical line shift is similar to the transient speed (ΔV/ΔT) of the vertical transfer pulses ΦV_1 through ΦV_4 which are applied to the vertical transfer electrodes 1032_1 through 1032_4 during the vertical blanking period. FIG. 49B illustrates a driving pulse using a rectangular pulse which rises vertically and falls vertically.
On the other hand, for example, operations at the time of electronic camera shake correction in an image-capturing device such as a video camera employing a CCD solid-state image-capturing device, and a CCD solid-state image-capturing device employing a frame interline transfer (FIT) system for broadcasting business need to perform high-speed vertical transfer during the vertical blanking period.
Also, an arrangement has been proposed wherein a CCD image-capturing device performs vertical line shift using four types of vertical transfer pulses during the horizontal blanking period (e.g., see FIG. 3 of Japanese Unexamined Patent Application Publication No. 2000-138943).
Incidentally, heretofore, with the above CCD solid-state image-capturing device 1030, vertical line shift and vertical high-speed transfer are driven by providing a vertical driving scan circuit having the same properties, i.e., a so-called vertical driver in the driving circuit 1004, and a high-speed CMOS-type vertical driver is commonly employed. Accordingly, when performing this vertical transfer during a horizontal valid scan period, noise (coupling noise) occurs due to crosstalk within the CCD solid-state image-capturing device 1030 at the moment of the vertical transfer pulses (ΦV_1 through ΦV_4) being applied.
In other words, when performing vertical transfer during a horizontal valid scan period, transient speed is fast at the leading and trailing edges of a driving waveform, i.e., the inclination ΔV/ΔT of the leading and trailing edges of the vertical transfer pulses (ΦV_1 through ΦV_4) is great, so crosstalk noise is superimposed upon a CCD output signal, and consequently, image noise of vertical lines appears. That is to say, deterioration in image quality occurs (noise occurs) due to the fast transient speed of a driving waveform. With embodiments, description will be made further in detail regarding this point, but the cause thereof is that the transient fluctuation of driving voltage as to one electrode interferes driving voltage as to other electrodes.
Accordingly, heretofore, in order to prevent this deterioration in image quality, vertical driving (vertical transfer) has been performed during a period other than the horizontal valid scan period. That is to say, in the event of performing vertical line shift, application of the vertical transfer pulses (ΦV_1 through ΦV_4) has no adverse effect on an image during the horizontal blanking period alone, so with an existing CCD solid-state image-capturing device, vertical transfer for vertical line shift has been performed during this horizontal blanking period.
The TV system defines a horizontal blanking period, so when TV was mainstream, it was sufficient that vertical line shift can be performed within the horizontal blanking period. However, when attempting to perform multiple pixelating or increased frame rates aside from the television system, the horizontal blanking period necessary for vertical line shift becomes a waste of time, which has impeded increased frame rates.
In order to realize increased frame rates, it is necessary to reduce the horizontal blanking period, but which needs to perform vertical line shift at high speed, and therefore, it becomes necessary to reduce the resistance of transfer electrodes. In order to realize reduction in resistance, an arrangement can be conceived wherein an electrode cross-sectional area is expanded as one technique, but it is difficult to expand this in the lateral direction (areal direction), there is the need to thicken the film thickness of the transfer electrodes. However, thickening the film thickness of the transfer electrodes causes a step around a center opening to increase in height, and when light enters there, vignetting of oblique light occurs, which causes a problem such as deterioration in sensitivity and occurrence of shading, and accordingly it is difficult to realize improvement in vertical transfer speed.
As described above, when increasing frame rate, with electronic equipment such as a digital camera or the like employing a CCD solid-state image-capturing device of a non-television system, even if the output rate of a signal is increased, the horizontal blanking period increases, and accordingly, it is difficult to obtain high speed exceeding a certain speed.
In order to solve such a problem, the present applicant has proposed an arrangement for extremely reducing the horizontal blanking period, and realizing increased frame rates (see Japanese Unexamined Patent Application Publication No. 2005-269060).
With the arrangement described in this Japanese Unexamined Patent Application Publication No. 2005-269060, a driving clock waveform having the inclination of the leading and trailing edges serving as transient speed V/T (wherein V represents voltage and T represents time), i.e., a pulse signal having a smooth moderate inclination is particularly employed as a transfer pulse, thereby supplying this to transfer electrodes serving as a capacitive reactance load. Thus, with a high-pixel CCD, a frame rate can be increased with a low clock rate by performing vertical transfer during a valid pixel period, but which needs to supply a pulse signal having a smooth and moderate inclination.
However, though removal of fixed pattern noise in darkness has been performed with the above method, since digitalization of expensive single-lens reflex cameras has advanced, time loss for capturing consecutively causes a problem, a mode not performing removal of difference of fixed pattern noise in darkness has been demanded.
However, at this time, with an existing CCD-built-in substrate bias circuit, hot carrier and luminescence proportional to an electric current flowing into the junction between the base and emitter of the NPN transistor 3 at the last stage remain, and the hot spot phenomenon deteriorates the image.
Note that the term “hot spot” means a phenomenon wherein unnecessary electric charge has accumulated circularly on the sensor centered on a place where hot carrier or luminescence occurs, and projected so as to emit light.
An advantage of the present invention is that hot spots can be prevented from occurring, and a solid-state image-capturing device capable of preventing deterioration in images, and the driving method thereof, and a camera, can be provided.
With the technology disclosed in Japanese Unexamined Patent Application Publication No. 2004-328203, a storage transfer configuration for two-phase driving assuming driving of moving images and still images in a digital still camera is employed, so it is necessary to perform transfer during a period wherein the driving pulse is at a low level, the duty ratio thereof also needs to be set to one of the number of driving phases.
Therefore, the electric charge storage amount thereof is the same as that in two phases, i.e., only the storage portion of one gate, and also the driving amplitude thereof is the same as that in two phases, and accordingly, it is difficult to realize enlargement of dynamic range and reduction in electric power.
That is to say, with the technology disclosed in Japanese Unexamined Patent Application Publication No. 2004-328203, multiple gate storage such as normal multi-phases driving is not employed, it is difficult to realize improvement in handling electric charge amount, and reduction in electric power due to reduction in amplitude.
Alternatively, a so-called multi-phases driving system such as three-phase driving or the like which is capable of low-voltage driving as compared with a two-phase driving system has been proposed.
FIG. 15 illustrates driving signal examples of three-phase driving. H1, H2, and H3 denote driving pulses, RG denotes a reset gate pulse, CCDout denotes output of a CCD, and SHP and SHD denote sampling and holding pulses.
As illustrated in FIG. 15, with a common three-phase driving system, there are disadvantages such as a crosstalk noise problem at a CDS sampling portion, difficulty in ensuring a data output period, and so forth.
That is to say, with normal multi-phases driving, according to operations such as transfer and storage, in a state in which at least one gate is at a low level, another one gate is changed for transfer, so there is a period wherein two gates go to low level.
Such multi-phases successive driving causes transition portions to increase, which has not been employed for driving of a horizontal CCD for performing sampling of a signal due to a crosstalk noise problem.
With Japanese Patent No. 3440722, crosstalk noise improvement technology using three-phase driving has been disclosed.
However, with the technology disclosed in Japanese Patent No. 3440722, it is necessary to perform transfer only during a narrow reset period, and accordingly, which is unsuitable for increase in speed.
An advantage of the present invention is that an electric-charge transfer device, solid-state image-capturing device, and a camera, and a method for driving a solid-state image-capturing device are provided, whereby it is possible to realize prevention of crosstalk and increase in speed while maintaining multi-phases original advantages, such as improvement in the amount of handling electric charge, and reduction in electric power due to reduction in amplitude.